[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend

[Andrei Safronov via llvm-dev]

Hello, James,

Thank you for your explanations, this is really helpful information. I 
will include this stages(or maybe similar) of integration process into 
my near-term plan and will inform you about progress in implementation.

Best regards, Andrei Safronov

09.03.2019 2:12, James Y Knight пишет:
> Yes, exactly.
>
> It's not important to follow exactly the same breakup as the RISCV 
> target, but it makes sense to follow roughly the same order of work.
>
> That is, the overall stages you'll want to tackle are going to be 
> something like:
> 1. Initial addition of the target, triple parsing, etc. (riscv patches 
> #2 through #4)
> 2. Working MC for the baseline ISA, (#5 through #11).
> 3. Codegen for the baseline ISA (#12-#32)
> 4. MC layer for ISA extensions (#33-#41)
> 5. Codegen for ISA extensions, and further fixes throughout (#42-...)
>
> Having patches that are small enough to be usefully-reviewable is very 
> helpful, and each patch should have a full set of test-cases included 
> testing its functionality (as much as is feasible).
>
> But it's also important to be able to see enough of the implementation 
> to have the necessary context to sanely review. So, that's why I 
> suggest that your initial goal should be to create a set of patches 
> fully-implementing just the first two items on that list, and post 
> them for review at the same time. After that's committed, move on to 
> extracting patches for further functionality, adding tests, and 
> posting for review as you go.