[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend

[Anmol Paralkar (anmparal) via llvm-dev]

Hello Andrei,

Thank you for the LLVM Xtensa work and the post. Cisco Systems would be glad to support any upstreaming effort for this work in terms of reviews, tests, object file generation, further development, etc.

Best Regards,
Anmol P. Paralkar

From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Andrei Safronov via llvm-dev <llvm-dev at lists.llvm.org>
Reply-To: Andrei Safronov <safronov at espressif.com>
Date: Wednesday, March 6, 2019 at 5:30 AM
To: "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org>
Subject: [llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend

Hello,

I'm from Espressif Systems company, software department. Our company develops processors based on Xtensa architecture like ESP32 and ESP8266. We propose the integration of a backend targeting Xtensa architecture.

We started to develop LLVM Xtensa backend almost a year ago. The reason was that we saw a demand from our large developers community. Currently only GNU compiler supports Xtensa architecture. The company has approved me to develop and maintain Xtensa backend.

We already have the initial version of the Xtensa backend, based on LLVM Compiler Infrastructure, release 6.0.0. It was successfully tested using GCC torture testsuite and multiple applications.

These are the links to LLVM and Clang repositories.

https://github.com/espressif/llvm-xtensa
https://github.com/espressif/clang-xtensa

Current version can generate Xtensa assembly code as output, not object files yet, and has to be used together with GNU Binutils and GCC-built libraries to create object and binary files.

Xtensa backend features implemented:

- Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, XtensaSubTarget.cpp)
- ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, XtensaREgisterInfo.td)
- Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp)
- ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, XtensaAsmParser.cpp)

Xtensa architecture features implemented in compiler:

- Xtensa Core Architecture instructions
- Code Density option
- Windowed Register option
- Floating-Point Coprocessor option
- Boolean option (only a subset of instructions)
- Thread Pointer option
- atomic operations

Current Xtensa target list:

- support Xtensa LX6 target (ESP32) by default

Compiler optimization levels include O0/O1/O2/O3/Os options.

With LLVM community approval, my next plans will be

- rebasing on the upstream version of LLVM.
- object code generation (XtensaMC package)
- implement test cases
- support for LX106 target (ESP8266)
- improvements of generated code performance
- support for zero-overhead loop option
- MAC16 option

There were some discussions about implementation of the Xtensa backend and attempt to implement it:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html
http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html

Also there were attempts to implement a LLVM Xtensa backend, but recently I found only one actual link:
https://github.com/jdiez17/llvm-xtensa

All comments and suggesions are welcome!

Andrei Safronov
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