[llvm-dev] [RFC] Vector Predication
Jacob Lifshay via llvm-dev
llvm-dev at lists.llvm.org
Fri Feb 1 02:10:36 PST 2019
On Fri, Feb 1, 2019 at 1:54 AM Simon Moll <moll at cs.uni-saarland.de> wrote:
> On 1/31/19 11:20 PM, Jacob Lifshay wrote:
> We're in-progress designing a RISC-V extension (
> that would have variable-length vectors of short vectors (1 to 4):
> <VL x <4 x float>>
> where each predicate bit masks out a whole short vector. We're using this
> extension to vectorize graphics code where where variables in the
> pre-vectorization code are short vectors.
> So, vectorizing code like:
> for(int i = 0; i < 1000; i++)
> vec4 color = colors[i];
> vec3 normal = normals[i];
> color.rgb *= fmax(0.0, dot(normal, light_dir));
> colors[i] = color;
> I'm planning on passing already vectorized code into LLVM and using LLVM
> as a backend for optimization and JIT code generation.
> Do you think the EVL proposal would support an ISA like this as it's
> currently written (by pattern matching on predicate expansion and
> vector-length multiplication)?
> Or, do you think the EVL proposal would need modification to effectively
> support this (by adding a element group size argument to EVL intrinsics or
> We could untie the mask length from the data length:
> %result = call <scalable 4 x float> @llvm.evl.fsub.v4f32(<scalable 4 x
> float> %x, <scalable 4 x float> %y, <scalable 1 x i1> %M, i32 %L)
> would then indicate the the mask %M applies to groups of "4 / 1" float
Sounds good to me. I haven't checked if the current code allows for that.
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