[llvm-dev] Guidance on working with the NVIDIA GPU back-end

[Dmitry Mikushin via llvm-dev]

Unlimited number of registers in PTX ISA means there is no any meaningful
register allocation at all. That is, it makes no sense trying to limit
something, which does not exist. NVPTX is lowered further by ptxas into
physical registers, but it is out of the scope of LLVM.

Kind regards,
- Dmitry.


пн, 16 дек. 2019 г. в 17:29, CoffeeBeforeArch via llvm-dev <
llvm-dev at lists.llvm.org>:

> Hi all,
>
> I'm primarily a hardware person but would like to do some
> compiler-architecture co-design research. Are there any good references for
> the NVPTX backend? I'd like to change that backend to have a limited number
> of physical registers rather than an unlimited number of virtual ones (for
> more realistic modeling in a uarch simulator).
>
> Being able to do register allocation and other optimizations on the
> virtual ISA (PTX) would be incredibly useful to the research community.
>
> Thanks in advance,
>
> --Nick
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