[llvm-dev] [A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM

[Jie Zhou via llvm-dev]

Hi Craig,

Thanks very much. I rechecked the ARMv7-M manual and found that the encoding of tADDi8
(entry A7.7.3, Encoding T2; ARM DDI 0403E.b) only has 3 bits for the register,
which explains why only R0 - R7 are allowed.

- Jie

On Apr 14, 2019, at 15:39, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:

It's in ARMRegisterInfo.td

// Thumb registers are R0-R7 normally. Some instructions can still use
// the general GPR register class above (MOV, e.g.)
def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
  let DiagnosticString = "operand must be a register in range [r0, r7]";
}

~Craig


On Sun, Apr 14, 2019 at 12:38 PM Jie Zhou <jzhou41 at cs.rochester.edu<mailto:jzhou41 at cs.rochester.edu>> wrote:
Hi Craig,

Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7?
I tried to search in ARMInstrThumb.td but couldn’t find it.

Thanks,
- Jie

On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:

I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2 instead of t.

The definition of tADDi8 looks like this. Where tGPR specifically means R0-R7.

  def tADDi8 :                    // A8.6.4 T2
    T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
                      (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
                      "add", "\t$Rdn, $imm8",
                      [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
                      Sched<[WriteALU]>;

~Craig


On Sun, Apr 14, 2019 at 12:21 PM Jie Zhou <jzhou41 at cs.rochester.edu<mailto:jzhou41 at cs.rochester.edu>> wrote:
Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2.
It has 12 regular registers (R0 - R12), and R8 - R12 are used.
I can generate mov instruction that from/ R8-R12 to/from R0-R6.
From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html<https://urldefense.proofpoint.com/v2/url?u=http-3A__infocenter.arm.com_help_index.jsp-3Ftopic-3D_com.arm.doc.dui0068b_ch03s03s01.html&d=DwMFaQ&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=KAtyTEI8n3FritxDpKpR7rv3VjdmUs0luiVKZLb_bNI&m=_fpYL_7E5zOQ4DZeiPmiSOgKp7KxZ5mAZVh9wB6CxUY&s=1r2JmIRDr3fxySkwnQU16zv8ySZfoc3nUtLdCcwb4gw&e=>
R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot
use them arbitrarily. The fact that we can use it to generate mov instructions but
not add/sub and push/pop confuses me.

- Jie

On Apr 14, 2019, at 14:55, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote:

I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7.

tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument.

~Craig


On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:
Hi all,

I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird.
For an add, when I use

        BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm).

if reg is R0 - R7, everything is fine: I would get something like

        adds r1, 4

But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get

        adds r0, 4

rather than

        adds r8, 4.

Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0 - R7, but
for registers whose number are greater than R7, the generated asm code doesn’t have it. For example,

        BuildMI(……, TII->get(ARM::tPUSH), R8)…..

would give me

        push {}

Is this a bug in the LLVM ARM code generator? Or is there a reason why we cannot use big-number registers for add/sub and push/pop?

Thanks,
- Jie
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