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Hi Craig,
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<div class="">Thanks very much. I rechecked the ARMv7-M manual and found that the encoding of tADDi8 </div>
<div class="">(entry A7.7.3, Encoding T2; ARM DDI 0403E.b) only has 3 bits for the register, </div>
<div class="">which explains why only R0 - R7 are allowed.</div>
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<div class="">- Jie</div>
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<div class="">On Apr 14, 2019, at 15:39, Craig Topper <<a href="mailto:craig.topper@gmail.com" class="">craig.topper@gmail.com</a>> wrote:</div>
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<div dir="ltr" class="">It's in ARMRegisterInfo.td
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<div class="">// Thumb registers are R0-R7 normally. Some instructions can still use</div>
<div class="">// the general GPR register class above (MOV, e.g.)</div>
<div class="">def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {</div>
<div class=""> let DiagnosticString = "operand must be a register in range [r0, r7]";</div>
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<div dir="ltr" class="gmail_signature">~Craig</div>
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<div dir="ltr" class="gmail_attr">On Sun, Apr 14, 2019 at 12:38 PM Jie Zhou <<a href="mailto:jzhou41@cs.rochester.edu" class="">jzhou41@cs.rochester.edu</a>> wrote:<br class="">
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<div style="overflow-wrap: break-word;" class="">Hi Craig,
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<div class="">Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7?</div>
<div class="">I tried to search in ARMInstrThumb.td but couldn’t find it.</div>
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<div class="">Thanks,</div>
<div class="">- Jie<br class="">
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<div class="">On Apr 14, 2019, at 15:28, Craig Topper <<a href="mailto:craig.topper@gmail.com" target="_blank" class="">craig.topper@gmail.com</a>> wrote:</div>
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<div dir="ltr" class="">I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2 instead of t.
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<div class="">The definition of tADDi8 looks like this. Where tGPR specifically means R0-R7.</div>
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<div class=""> def tADDi8 : // A8.6.4 T2</div>
<div class=""> T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),</div>
<div class=""> (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,</div>
<div class=""> "add", "\t$Rdn, $imm8",</div>
<div class=""> [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,</div>
<div class=""> Sched<[WriteALU]>;</div>
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<div dir="ltr" class="gmail-m_-4165026908401281747gmail_signature">~Craig</div>
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<div dir="ltr" class="gmail_attr">On Sun, Apr 14, 2019 at 12:21 PM Jie Zhou <<a href="mailto:jzhou41@cs.rochester.edu" target="_blank" class="">jzhou41@cs.rochester.edu</a>> wrote:<br class="">
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<div class="">Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2.
<div class="">It has 12 regular registers (R0 - R12), and R8 - R12 are used. </div>
<div class="">I can generate mov instruction that from/ R8-R12 to/from R0-R6. </div>
<div class="">From this ARM page <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__infocenter.arm.com_help_index.jsp-3Ftopic-3D_com.arm.doc.dui0068b_ch03s03s01.html&d=DwMFaQ&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=KAtyTEI8n3FritxDpKpR7rv3VjdmUs0luiVKZLb_bNI&m=_fpYL_7E5zOQ4DZeiPmiSOgKp7KxZ5mAZVh9wB6CxUY&s=1r2JmIRDr3fxySkwnQU16zv8ySZfoc3nUtLdCcwb4gw&e=" target="_blank" class="">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html</a></div>
<div class="">R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot </div>
<div class="">use them arbitrarily. The fact that we can use it to generate mov instructions but</div>
<div class="">not add/sub and push/pop confuses me.</div>
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<div class="">- Jie<br class="">
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<div class="">On Apr 14, 2019, at 14:55, Craig Topper <<a href="mailto:craig.topper@gmail.com" target="_blank" class="">craig.topper@gmail.com</a>> wrote:</div>
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<div dir="ltr" class="">I don't know much about ARM. But it looks like tADDi8 is a Thumb instruction and it can only use R0-R7.
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<div class="">tPUSH probably as a similar issue. But it's also a store instruction and doesn't produce a register output. So you should use the form of BuildMI that doesn't take a register as its last argument.<br class="">
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~Craig</div>
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<div dir="ltr" class="gmail_attr">On Sun, Apr 14, 2019 at 11:17 AM Jie Zhou via llvm-dev <<a href="mailto:llvm-dev@lists.llvm.org" target="_blank" class="">llvm-dev@lists.llvm.org</a>> wrote:<br class="">
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Hi all,<br class="">
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I’m trying to insert some add/sub and push/pop instructions in a MachineFunction pass for ARMv7-M. However, I encountered something weird.<br class="">
For an add, when I use <br class="">
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BuildMI(….., TII->get(ARM::tADDi8), reg).addReg(reg).addReg(reg).addImm(imm).<br class="">
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if reg is R0 - R7, everything is fine: I would get something like<br class="">
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adds r1, 4<br class="">
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But if I use R8 - R12 as the reg in the BuildMI, I wouldn’t get the correct register in the assembly code. For example, when I pass R8 to it, I would get
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adds r0, 4<br class="">
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rather than<br class="">
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adds r8, 4.<br class="">
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Similar problems happen to push and pop instructions. I can create a push/pop if the register list only contains registers R0 - R7, but<br class="">
for registers whose number are greater than R7, the generated asm code doesn’t have it. For example,
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BuildMI(……, TII->get(ARM::tPUSH), R8)…..<br class="">
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would give me <br class="">
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push {}<br class="">
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Is this a bug in the LLVM ARM code generator? Or is there a reason why we cannot use big-number registers for add/sub and push/pop?
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Thanks,<br class="">
- Jie<br class="">
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