[llvm-dev] How to add Loongson ISA for Mips target?

[Leslie Zhai via llvm-dev]

Hi Daniel,

Thanks for your kind response!

Loongson 3A3000 is based on MIPS64r2

https://en.wikipedia.org/wiki/Loongson#Loongson_3

I will look at ASE_* class,  thanks for your teaching!

And please point out my fault about my requirement 
http://lists.llvm.org/pipermail/llvm-dev/2018-September/125895.html


在 2018年09月06日 23:18, Daniel Sanders 写道:
> - my old email address.
>
> The ISA_* classes might not be the best choice for this. There's an 
> overall hierarchy and ordering to the ISA_* classes since they 
> represent the generations of the MIPS ISA. If these extensions are 
> available in Loongson chips based on MIPS32r1 and MIPS32r2 for 
> example, it becomes difficult to describe with ISA_* classes without 
> duplicating instruction definitions or setting up complicated subsets 
> (like we had to for MIPS32r6 to deal with the instruction removals).
>
> I would recommend the ASE_* classes which are intended for application 
> specific extensions. These are used for optional extensions to the 
> MIPS ISA such as MSA or DSP, but are also used for vendor specific 
> extensions to the MIPS ISA such as cnMIPS. The ASE_CNMIPS class and 
> the Proc<"octeon", ...> record are good examples that show how 
> Cavium's extensions to the MIPS ISA were included.
>
>> On 6 Sep 2018, at 04:01, Simon Atanasyan via llvm-dev 
>> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
>> Hi,
>>
>> LLVM MIPS backend now supports different MIPS ISA like mips1, mips2,
>> mips3, mips32, mips32r6 etc. If Loongson ISA just add a few new
>> instructions I think you do not have to add a new subtarget. Take a
>> look at MipsInstrInfo.td file. In that file there are multiple
>> ISA_MIPSxxx classes. Take for example ISA_MIPS3 and search it through
>> *.td files. Here is an example of instruction definition specific to
>> mips3:
>> [[
>>  def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
>>              bitconvert>, MFC1_FM<5>, ISA_MIPS3;
>> ]]
>>
>> More general and complete guide can be found here:
>> http://llvm.org/docs/WritingAnLLVMBackend.html
>>
>> On Thu, Sep 6, 2018 at 1:01 PM Leslie Zhai <zhaixiang at loongson.cn 
>> <mailto:zhaixiang at loongson.cn>> wrote:
>>>
>>> Hi LLVM developers,
>>>
>>> GCC[1] is able to use Loongson ISA[2] for instruction selection:
>>>
>>> $ cat hello.c
>>> #include <stdio.h>
>>>
>>> int main(int argc, char *argv[]) {
>>>   printf("Hello World\n");
>>>   return 0;
>>> }
>>>
>>> $ gcc -O0 -S hello.c
>>>
>>> $ cat hello.s
>>>     .file    1 "hello.c"
>>>     .section .mdebug.abi64
>>>     .previous
>>>     .nan    legacy
>>>     .gnu_attribute 4, 1
>>>     .abicalls
>>>     .rdata
>>>     .align    3
>>> .LC0:
>>>     .ascii    "Hello World\000"
>>>     .text
>>>     .align    2
>>>     .globl    main
>>>     .set    nomips16
>>>     .set    nomicromips
>>>     .ent    main
>>>     .type    main, @function
>>> main:
>>>     .frame    $fp,48,$31        # vars= 16, regs= 3/0, args= 0, gp= 0
>>>     .mask    0xd0000000,-8
>>>     .fmask    0x00000000,0
>>>     .set    noreorder
>>>     .set    nomacro
>>>     daddiu    $sp,$sp,-48
>>>     gssq    $31,$fp,32($sp)
>>>     sd    $28,24($sp)
>>>     move    $fp,$sp
>>>     lui    $28,%hi(%neg(%gp_rel(main)))
>>>     daddu    $28,$28,$25
>>>     daddiu    $28,$28,%lo(%neg(%gp_rel(main)))
>>>     move    $2,$4
>>>     sd    $5,8($fp)
>>>     sll    $2,$2,0
>>>     sw    $2,0($fp)
>>>     ld    $2,%got_page(.LC0)($28)
>>>     daddiu    $4,$2,%got_ofst(.LC0)
>>>     ld    $2,%call16(puts)($28)
>>>     move    $25,$2
>>>     .reloc    1f,R_MIPS_JALR,puts
>>> 1:    jalr    $25
>>>     nop
>>>
>>>     move    $2,$0
>>>     move    $sp,$fp
>>>     gslq    $31,$fp,32($sp)
>>>     ld    $28,24($sp)
>>>     daddiu    $sp,$sp,48
>>>     j    $31
>>>     nop
>>>
>>>     .set    macro
>>>     .set    reorder
>>>     .end    main
>>>     .size    main, .-main
>>>     .ident    "GCC: (GNU) 4.9.3 20150626 (Red Hat 4.9.3-8)"
>>>
>>> gssq and gslq are some instructions of Loongson ISA.  How to add
>>> Loongson ISA for Mips target?
>>>
>>> I just:
>>>
>>> * add loongson3a cpu in frontend
>>> https://github.com/xiangzhai/clang/commits?author=xiangzhai
>>>
>>> * initial Loongson3A subtarget skeleton.
>>>
>>> Are there some documents or papers?  Please teach me,  thanks a lot!
>>>
>>> 1. https://github.com/loongson-community/gcc
>>> 2. Chinese Simplified version
>>> http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user2.pdf
>>
>> --
>> Simon Atanasyan
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

-- 
Regards,
Leslie Zhai