[llvm-dev] Fw: How to define an instruction

Tue Nov 13 22:43:45 PST 2018

Thank you for answering my confusion.
I have another questions.
If I add  really instructions instead intrinsics ,can I reach my purpose? 
I guess ,the answer is "can't". I don't find the anything about how machine to do about instructions,especially "ALU" instructions.
Thank you again,
Tianhao Shen

On 11/14/2018 13:42，Craig Topper<craig.topper at gmail.com> wrote：
For the most part target specific intrinsics are black boxes to llvm. They're just a little bit better than using inline assembly. They're pretty much just a way to say from C code that you want to use a specific fancy hardware instruction that does some operation that's not easy to express concisely in C. So they get passed through llvm and just tell the backend to emit a specific opcode into the final binary.

lli  by default on x86 is a JIT compiler, it compiles llvm IR into native hardware instructions and makes the processor execute them. I believe you can force it to use an IR interpreter and not compile to native code, but I don't think it would support a target specific intrinsic in that mode.

~Craig

On Tue, Nov 13, 2018 at 7:27 PM Tianhao Shen <17862703959 at 163.com> wrote:

--------- Forwarded Message ---------

From： Tianhao Shen <17862703959 at 163.com>
Date： 11/14/2018 09:31
To： craig.topper at gmail.com <craig.topper at gmail.com>
Subject： Re: [llvm-dev] How to define an instruction
Hi, Craig
Thank you for replying to me.
I guess that you misunderstand my meaning about "can'r run". I just want to run my instruction by LLVM using  the commands "clang -O0 -emit-llvm test.c -S -o test.ll" and "lli test.ll".But now ,when I use "lli test.bc" , the result shows as following:
Stack dump:
0.Program arguments: lli test.ll 
LLVMSymbolizer: error reading file: No such file or directory
#0 0x000000000211b709 (lli+0x211b709)
#1 0x000000000211b79c (lli+0x211b79c)
#2 0x0000000002119496 (lli+0x2119496)
#3 0x000000000211b104 (lli+0x211b104)
#4 0x00007fe3d188a390 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x11390)
#5 0x00007fe3d1cba035
#6 0x0000000001b7ff7f (lli+0x1b7ff7f)
#7 0x0000000001a83d44 (lli+0x1a83d44)
#8 0x000000000126ee7b (lli+0x126ee7b)
#9 0x00007fe3d05e7830 __libc_start_main /build/glibc-Cl5G7W/glibc-2.23/csu/../csu/libc-start.c:325:0
#10 0x000000000126b799 (lli+0x126b799)
illegal instruction(core dump)

Can I do what I write above ?
You wrote "The compiler can't just make up a new instruction. ".What do you mean?   LLVM doesn't describe the calculation process, or scheduler model doesn't but other model does ? 
Thanks sincerely,
Tianhao Shen.
On 11/14/2018 01:55，Craig Topper<craig.topper at gmail.com> wrote：
What do you mean by can't be run? You can't just define your own instruction and execute it on real hardware. The behavior of an instruction is defined by the hardware manufacturer like Intel or AMD. The compiler can't just make up a new instruction. The scheduler model in LLVM is just a description of how many of the instruction can be done in parallel and how long it takes. It helps the compiler order instructions, but it doesn't provide any description of how the resulting bits are calculated.

~Craig

On Tue, Nov 13, 2018 at 4:50 AM Tianhao Shen via llvm-dev <llvm-dev at lists.llvm.org> wrote:

Hi,
I have some questions about instructions again.
I have add a DAG successfully,I think.Because what I do can be compiled to LLVM IR and binary file.
I guess, the schedule of an instruction tells the machine how to do . I don't konw if it's right.
For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication.
def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}",   [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32;
And in X86ScheduleXXX.td ,there is definition of Ports and so on.

My questions are here,as following:
1.whether the schedule of an instruction defines the machine how to do.
2.Why is there no "add" or "sub" instructions("ALU insturctions") in X86InstrArithmetic.td? How "ALU insturctions" define?
3. I use the WriteIMul32Reg in my insturction.In my imagination, my instruction should also be multiplication.But it doesn't work.(my instruction can be compiled but can't run) .why  can't it run? I think, it's no different with "IMUL32rr ".
Here is the result :
test.c shows as following:(the main content )
int a,b;
a=1;b=1;
a=a=__builtin_x86_max_qb (a,b); (the main content  )
test.ll shows as following:
  %0 = load i32, i32* %a, align 4
  %1 = load i32, i32* %b, align 4
  %2 = call i32 @llvm.x86.max.qb(i32 %1, i32 %2)
  store i32 %2, i32* %a, align 4  
when lli test.ll ,it goes wrong.

Here is my all code:
1. In llvm/include/llvm/IR/IntrinsicsX86.td : 
let TargetPrefix = "x86" in { 
def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">,
  Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [Commutative]>;
}
2. In llvm//tools/clang/include/clang/Basic/BuiltinsX86.def:  
BUILTIN(__builtin_x86_max_qb, "iii", "") 
3.In llvm/lib/Target/X86/X86ISelLowering.h:
max_qb,
4.In llvm/lib/Target/X86/X86IntrinsicsInfo.h:(IntrinsicsWithoutChain)
X86_INTRINSIC_DATA(max_qb, INTR_TYPE_2OP, X86ISD::max_qb, 0),
5.In llvm/lib/Target/X86/X86InstrInfo.td:
def X86max_qb : SDNode<"X86ISD::max_qb", SDTBinaryArithWithFlags,
                          [SDNPCommutative]>;
6.In X86InstrArithmetic.td: 
let Defs = [EFLAGS] in {
    let Constraints = "$src1 = $dst" in {
        let isCommutable = 1 in {
                def max_qb : I<0xF0,MRMSrcReg, (outs  GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb{w}\t {$dst, $src1,$src2|$dst, $src2,$src1}", [(set GR32:$dst,EFLAGS,(X86max_qb GR32:$src1, GR32:$src2))]>, Sched<[WriteIMul32Reg]>,OpSize32 ;
        }
    }
}

I know,this email is too long to read easily. But I hope you can read over and help me. 
Thanks sincerely,
Tianhao Shen

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