[llvm-dev] how to add a instruction

[Craig Topper via llvm-dev]

The main x86 encoding scheme doesn't allow 3 independent registers. You'll
have to switch to the VEX encoding scheme used by some of the newer
instuctions like ANDN, SHRX, SHLX, SARX. This allows 3 registers to be
encoded.

Add ", VEX_4V" to the end of your instruction definition.

~Craig


On Thu, Nov 8, 2018 at 2:43 AM Tianhao Shen <17862703959 at 163.com> wrote:

> Thank you for answering my questions.
> I don't understand how to disarm the constraints, because I want to my
>  instruction like  "c=max_qb(a,b)".
> Thank you again.
> Tianhao Shen.
>
> On 11/8/2018 01:33，Craig Topper<craig.topper at gmail.com>
> <craig.topper at gmail.com> wrote：
>
> The "Unhandled immediate encoding GR32" is fixed by the "let Constraints =
> "$src1 = $dst". That tells the disassembler, encoder, and register
> allocator that $src1 and $dst must always be the same physical register.
> This is true of all the basic X86 arithmetic instructions where one of the
> inputs is always overwritten by the output.
>
> ~Craig
>
>
> On Tue, Nov 6, 2018 at 11:26 PM Tianhao Shen via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi,every one.
>> I' in trouble again.
>> I want add a new intrinsic mapping a new instruction.
>>
>> I add the int_x86_max_qb as fllowing:
>> def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">, Intrinsic<[llvm_i32_ty],
>> [llvm_i32_ty, llvm_i32_ty], [Commutative]>;
>>
>> BUILTIN(__builtin_x86_max_qb, "iii", "")
>>
>> I define the intrinsic as Pseudo instruction,it succeed.
>>
>> But when mapping a new instruction.I don't know how to do.
>> In x86InstrArithmetic.td. I add ,(To make sure the Sched is right, I use
>> the WriteIMul16Reg )
>> def max_qb : I<0xF0,MRMSrcReg, (outs  GR32:$dst), (ins
>> GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set
>> GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32
>> ;
>> when compile LLVM , the error appears.
>> "[ 97%] Updating X86GenAsmWriter1.inc...
>> Unhandled immediate encoding GR32
>> Unhandled immediate encoding
>> "
>>
>> But when I write the same as the instruction IMUL32rr, there is no error
>> in compiling.(I don't use the EFLAGS at all, so I think it's wrong. Indeed,
>> it made a error when using it.)
>> let Defs = [EFLAGS] in {
>> let Constraints = "$src1 = $dst" in {
>> let isCommutable = 1 in {
>> def max_qb : I<0xF0,MRMSrcReg, (outs  GR32:$dst), (ins
>> GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set
>> GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32
>> ;
>> }
>> }
>>
>> What I don't understand is that how I define "let   in  ".
>> Thanks,
>> Tianhao Shen.
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>
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