[llvm-dev] Interprocedural register allocation. Status?

Wed May 30 14:43:21 PDT 2018

Hi Jon,
 I was looking at IPRA a while ago and then got pulled into other things. I completely missed Jonas’ questions on llvm-dev. Thanks Hal for pointing this out. I’ll take a look at this thread when I’m back at my laptop.

 I have one patch posted to fix a functional bug I found on PPC. Aside from that, I believe IPRA was functionally clean on PPC, but I need to do another round of testing to confirm. I also need to do another round of performance tests to make sure it doesn’t cause any performance regressions before enabling it.

 Sent from my iPhone using IBM Verse

 On May 30, 2018, 4:51:56 PM, hfinkel at anl.gov wrote:

 From: hfinkel at anl.gov
 To: jonathanchesterfield at gmail.com, llvm-dev at lists.llvm.org
 Cc: paulsson at linux.vnet.ibm.com, kbarton at ca.ibm.com, vivekvpandya at gmail.com
 Date: May 30, 2018, 4:51:56 PM
 Subject: Re: [llvm-dev] Interprocedural register allocation. Status?

   Hi, Jon, 
  I believe that the status is that it works, although there are some outstanding issues around conditionally-reserved registers on some targets, please see http://lists.llvm.org/pipermail/llvm-dev/2018-May/122884.html for some discussion of the outstanding issues.   
   -Hal  
      On 05/30/2018 02:31 PM, Jon Chesterfield via llvm-dev wrote: 

      There was a GSoC project in 2016, final report at  https://docs.google.com/document/d/1v-R7gB7Or4bPn0LW7d-yb1yla8jK3DVmTJNFVNYNu6k 

        Google doesn't show a lot of activity since. Has anyone taken this work further / put it near production? I'm interested in removing register spills around functions that are known to not clobber said registers. 

        Thanks! 

        Jon 

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  -- Hal FinkelLead, Compiler Technology and Programming LanguagesLeadership Computing FacilityArgonne National Laboratory

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