[llvm-dev] Generating a custom opcode from an LLVM intrinsic

[Gus Smith via llvm-dev]

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.

Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.

I'm trying to get an LLVM backend to generate this opcode during code
generation. My current plan is:

   1. During an LLVM pass, I'll detect a series of instructions which can
   be replaced with this new instruction. (The new instruction is a "cache
   compute" instruction -- in my passes, I replace a series of loads,
   operations, and stores with this single instruction.) This step is complete.
   2. I replace the series of instructions with an intrinsic. I have added
   an intrinsic using the instructions here
   <https://llvm.org/docs/ExtendingLLVM.html#adding-a-new-intrinsic-function>.
   This step is complete.
   3. During code generation, the intrinsic should be converted to this
   reserved opcode. This is where I'm stuck.

I'm stuck on step 3. I have two main questions that should unblock me:

Question 1: where is the code that maps from intrinsics to instructions?
The link above states:

"Add support to the .td file for the target(s) of your choice in
lib/Target/*/*.td. This is usually a matter of adding a pattern to the .td
file that matches the intrinsic, though it may obviously require adding the
instructions you want to generate as well. There are lots of examples in
the PowerPC and X86 backend to follow."

However, looking through these examples isn't illuminating anything for me.
Any more documentation or high-level explanation on this subject would be
really helpful. I have read something about "lowering" of intrinsics; not
sure if that's relevant.

Question 2: will I be able to generate this opcode directly from the
intrinsic, or will I have to add the opcode as an LLVM IR instruction and
specify how it gets compiled? I can imagine two options:
option 1: I can define a "translation" from intrinsic straight to an x86
opcode.
option 2: I can define a "translation" (perhaps in a .td file? I think
that's what they're used for) which translates my intrinsic into a new
instruction, and then I can define another translation which will map the
new instruction to my opcode during code gen. If this is the case, I'm not
sure there's any point to having an intrinsic; I should just add a new
instruction instead.

Hoping someone can help! As you can tell, I'm a little lost...the
documentation for LLVM is great, but it's a little above my level right now
:)

Gus Smith, PSU
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