[llvm-dev] generating multiple instructions for a single pattern

[Nagaraju Mekala via llvm-dev]

On Fri, Mar 2, 2018 at 4:59 PM, David Chisnall
<David.Chisnall at cl.cam.ac.uk> wrote:
> On 2 Mar 2018, at 11:09, Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>>   I am working on a target which requires to generated two
>> instructions for a single branch instruction.
>> ex:
>>   imm 1
>>   br r4,0xabcd
>>   branch address is 0x1abcd, imm has the upper 16 bits and br has
>> lower 16 bits.
>>
>>  Can anyone let me know how to write these kind of patterns in the
>> InstrInfo.td file.
>
> Do the two instructions need to be together?  Is one providing an operand via an implicit register?
>
> If the two are simply a sequence that must be emitted together, then the easiest thing to do is make it a pseudo and then expand it into two instructions later.  If one is really providing part of the operand via an implicit register, then it’s best to describe that directly and let the scheduler decide where to put the first instruction.
Thanks for the reply.
yes they are dependent if the branch immediate value is > 0xffff then
the imm instruction should generate other wise only "br" instruction
is enough.

Thanks,
Nagaraju
>
> David
>