[llvm-dev] Target hardware loop instruction via intrinsics
Jon Chesterfield via llvm-dev
llvm-dev at lists.llvm.org
Thu Jun 21 11:38:07 PDT 2018
That's a good idea, thanks!
On Thu, Jun 21, 2018 at 7:25 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> On 06/21/2018 01:07 PM, Jon Chesterfield via llvm-dev wrote:
> Hexagon has a MIR pass for detecting loops that map onto hardware support.
> I think a similar approach would be viable for my target but am put off by
> the complexity of determining whether a given loop is legal to transform.
> I think that it is easier to do this legality checking at the IR level
> (where we can take advantage of the ScalarEvolution analysis). This is what
> PowerPC does (see lib/Target/PowerPC/PPCCTRLoops.cpp). I recommend that
> you take this approach if possible.
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