[llvm-dev] Store Instruction pattern match

ComputerFreak via llvm-dev llvm-dev at lists.llvm.org
Sun Jun 17 19:06:52 PDT 2018

Hi, I am trying to develop new llvm backend based on RISCV architecture for practice.
using --debug option on llc tool, I got this error message.  
LLVM ERROR: Cannot select: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32
So I have questions on this problem.
1. Does this mean there is no SDNode matching the store pattern like that?  
2.  In LLVM language reference, the 'store' command pattern looks like this
store [volatile] <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !<index>][, !invariant.group !<index>]

Based on this pattern, I define the store instruction in my *InstrInfo.td like this
def STORE : MemStore_RISCVS<0b0100011, 0b010, "st", st, simm12, immSExt12, VR6Regs>; 
because In RISCV, store instruction has 2 registers and 12 bit immediate value.  
Bit in the log upside there, it seems the word 'undef' makes the problem. ( This is just my assumption, so it could be wrong. If i am wrong, please correct me)
Should I change my InstrInfo.td file then...?  
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180618/1d88c749/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: llc.log
Type: text/x-log
Size: 6988 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180618/1d88c749/attachment.bin>

More information about the llvm-dev mailing list