<html><head><style>p{margin-top:0px;margin-bottom:0px;}</style></head><body><div style="font-size:10pt; font-family:Gulim, sans-serif;"><p>Hi, I am trying to develop new llvm backend based on RISCV architecture for practice.</p><p>using --debug option on llc tool, I got this error message. </p><p> </p><p>LLVM ERROR: Cannot select: t4: ch = store<ST4[%1]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32</p><p> </p><p>So I have questions on this problem.</p><p>1. Does this mean there is no SDNode matching the store pattern like that? </p><p> </p><p>2. In LLVM language reference, the 'store' command pattern looks like this</p><pre>store [volatile] <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !<index>][, !invariant.group !<index>] <br><br>Based on this pattern, I define the store instruction in my *InstrInfo.td like this<br></pre><p>def STORE : MemStore_RISCVS<0b0100011, 0b010, "st", st, simm12, immSExt12, VR6Regs>; </p><p>because In RISCV, store instruction has 2 registers and 12 bit immediate value. </p><p>Bit in the log upside there, it seems the word 'undef' makes the problem. ( This is just my assumption, so it could be wrong. If i am wrong, please correct me)</p><p>Should I change my InstrInfo.td file then...? </p></div></body></html><table style='display:none'><tr><td><img src="https://mail.naver.com/readReceipt/notify/?img=i%2FYsWzeTM6FvFzF0pxKYpo2Xp4EdFAJvF6JCKqkvMxbrp6i4Kqg9aEIo%2BrkSKoE5W4d5W4C5bX0q%2BzkR74FTWx%2FsWzwrWL9vpBpgWz0q%2BHK5WzwrWLlTb4b%3D.gif" border="0"/></td></tr></table>