[llvm-dev] [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths

via llvm-dev llvm-dev at lists.llvm.org
Tue Jun 5 12:15:49 PDT 2018

>> I'm not so sure.  iota is a generally useful operation and scaling it to
>> various step values is also useful.  It's used often for strided memory
>> access, which would be done via gather/scatter in LLVM but generating a
>> vector GEP via stepvector would be convenient and convey more semantic
>> information than, say, loading a constant vector of indices to feed the
>> GEP.
> My point is that those patterns will be generated by C-level
> intrinsics or IR optimisation passes (like vectorisers), so they have
> a specific meaning in that context.
> What I fear is if some other pass like CSE finds the patterns out and
> common them up at the top of the function/BB and then the back-end
> loses sight of what that was and can't generate the step increment
> instruction in the end.

Got it.  Graham hit this point as well.  I took your suggestion as
"fusing" the iota/scale/offset together.  I would still want to be able
to generate things like stepvector without scaling and adding offsets (I
suppose a scale of 1 and offset of 0 would be ok, but ugly).  I don't
really care if we prevent CSE of such things.


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