[llvm-dev] [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths

[Renato Golin via llvm-dev]

On 5 June 2018 at 18:38,  <dag at cray.com> wrote:
> I thought stepvector was also always step one, as Graham states a
> multiply by a constant splat must be used for other step values.

You're right! Sorry, it's been a while. Step-vector is a simple iota,
the multiplier and offset come form the operations.


> I'm not so sure.  iota is a generally useful operation and scaling it to
> various step values is also useful.  It's used often for strided memory
> access, which would be done via gather/scatter in LLVM but generating a
> vector GEP via stepvector would be convenient and convey more semantic
> information than, say, loading a constant vector of indices to feed the
> GEP.

My point is that those patterns will be generated by C-level
intrinsics or IR optimisation passes (like vectorisers), so they have
a specific meaning in that context.

What I fear is if some other pass like CSE finds the patterns out and
common them up at the top of the function/BB and then the back-end
loses sight of what that was and can't generate the step increment
instruction in the end.

-- 
cheers,
--renato