[llvm-dev] Implement VLIW Backend on LLVM (Assembler Related Questions)

[via llvm-dev]

I believe the assembler parser does not immediately emit the object-file encoding, but produces an internal machine-instruction form that is later encoded and emitted.  This should give you an opportunity to make choices about encoding after the parsing is complete.

I don't know enough about how instruction syntax is specified to answer your other questions.
--paulr

From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Cy Cheng via llvm-dev
Sent: Thursday, December 06, 2018 8:47 PM
To: llvm-dev at lists.llvm.org
Subject: [llvm-dev] Implement VLIW Backend on LLVM (Assembler Related Questions)

Hello,

I want to implement LLVM backend for a specific VLIW hardware. I am working on defining its instruction set, and assembly language.

The hardware has two pipelines, int and float. Each pipeline can do 3 operations/cycle, 3 operations forms an instruction.

One of the Integer Instruction looks like this:
    add Ri, Rj, Rk; add Rl, Rm, Rn; add Ro, Rp, Rq

An int instruction and a float instruction forms a VLIW instruction (bundle), e.g.

{
    add Ri, Rj, Rk; add Rl, Rm, Rn; add Ro, Rp, Rq
    fadd Fi, Fj, Fk; fadd Fl, Fm, Fn; fadd Fo, Fp, Fq
}

I want to express above concept in this way:
// Assembly Language
{
    add Ri, Rj, Rk
    add Rl, Rm, Rn
    add Ro, Rp, Rq
    fadd Fi, Fj, Fk
    fadd Fl, Fm, Fn
    fadd Fo, Fp, Fq
}

Q1:
My first question is, the instruction encoding can only be determined after parser has finished parsing the entire bundle.

e.g. When parser see "add Ri, Rj, Rk", it generates one encoding, but when parser see another "add Ri, Rj, Rk", it will modify previously generated encoding.

I would like to know can LLVM's assembler support this?
Or I should define my instruction in this way:
   add_type1 Ri, Rj, Rk
   add_type2 Ri, Rj, Rk, Rl, Rm, Rn
   add_type3 Ri, Rj, Rk, Rl, Rm, Rn, Ro, Rp, Rq

Q2.
Some of the instructions need to setup additional configuration, e.g.
{
    scache wa   ; Set cache mode: write allocate
    ssize 64    ; Set write size = 64 bits
    sendian big ; Set big endian writing
    store R0, 0x1000000 ; Write "R0" to 0x1000000
}

So, again, parser has to parse the entire bundle to generate correct encoding.
Or I should define my instruction in this way:

store R0, 0x1000000, wa, 64, big, .... (10 options can be set)

Q3.
The destination register can be omitted, e.g.
    add , Rj, Rk

So can I use this form to express omitting destination, or I should define new instruction for it?
e.g.
    add_no_dest Rj, Rk

Q4.
Can I define the instruction which has the same name but with different count of operands, e.g.
    fadd Fi, Fj, Fk
    fadd Fl, Fm, Fn, rounding_mode

So fadd has two versions
(a) normal rounding
(b) special rounding mode

Or I should define it in this way:
fadd
fadd_round_mode1
fadd_round_mode2
..
fadd_round_mode15
(16 rounding mode)

Thank You,
CY
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