[llvm-dev] Branch relaxation at assembler level (RISCV)

Friedman, Eli via llvm-dev llvm-dev at lists.llvm.org
Tue Dec 4 12:13:39 PST 2018

On 12/3/2018 2:45 PM, Paolo via llvm-dev wrote:
> Hi all,
> I'm trying to implement the same branch relaxation mechanism implemented
> in CodeGen in the MC layer of RISCV.
>    beqz t1, L1
>    =>
>    bnez t1, L2
>    j L1
> That's because LLVM does not apply the CodeGen optimizations when
> compiling directly from assembly code.
> What I'd like to do would be to add a pass that does that on the MC
> instructions or at least to find a way to implement this relaxation in
> the MC assembler.
> Any suggestions on where/how to do it? Or any existing fixes?

The RISCV assembler already has code for similar transforms; see 
RISCVAsmBackend::mayNeedRelaxation and 
RISCVAsmBackend::relaxInstruction.  The only tricky bit is that the 
relaxation interface doesn't expect one instruction to be relaxed to two 
instructions... probably not too hard to change, though, if necessary.

That said, I'm a little skeptical this is actually a good idea; the more 
"smart" the assembler is, the harder it becomes to understand what it's 
doing. No other in-tree target does this sort of transform.


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