[llvm-dev] RFC: AArch64 SVE Assembler/Disassembler patches

[Sander De Smalen via llvm-dev]

Hi,

Probably a lot of you are attending interesting talks at LLVM Dev meeting this week, so I hope this message isn't completely lost in all the excitement.

In the past month we have carved off our changes to LLVM's assembler/disassembler that implement the AArch64 SVE instruction set [1]. These changes are split these up into individual patches that purely focus on the assembler and disassembler and have no link to the IR (yet). We would like to start sharing these patches with upstream LLVM.

I have made a best effort to split these changes into small, manageable patches (or patch sets) that can be reviewed and applied individually over time, where each patch/patch-set aims to add a new instruction (or variant or addressing mode for an instruction). Each patch-set has corresponding tests to cover the added instruction.

A first set of patches that implement SVE (unpredicated) ADD/SUB instructions can be found in Phabricator:
- https://reviews.llvm.org/D39087
- https://reviews.llvm.org/D39088
- https://reviews.llvm.org/D39089
- https://reviews.llvm.org/D39090
- https://reviews.llvm.org/D39091

Please let me know if you have any comments or suggestions to make sharing/reviewing these patches easier. I'm open to any feedback to get patches in the right shape!

Sander

[1]  The AArch64 SVE specification and related documents can be found here:
  https://developer.arm.com/products/software-development-tools/hpc/sve
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