[llvm-dev] Questions about code-size optimizations in ARM backend

[Momchil Velikov via llvm-dev]

On Tue, Nov 7, 2017 at 5:02 PM, Gabor Ballabas via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> I started to work on code-size improvements on ARM target by comparing GCC
> and LLVM generated code.
> My first candidate was switch-case lowering.
> I also created a Bugzilla issue for this topic:
> https://bugs.llvm.org/show_bug.cgi?id=34902
> The full example code and the generated assembly for GCC and for LLVM is in
> the Bugzilla issue.
>
> My first idea was to simplify the following instruction pattern
>         lsl     r0, r0, #2
>        ldr     pc, [r0, r1]
> to this:
>         ldr     pc, [r1, r0, lsl #2]
>

Your post prompted me to finally send this patch that I had laying
around since Jan/Feb :/ (https://reviews.llvm.org/D39752)

The LDR-with-shift instruction that we want to emit is defined in
ARMInstrInfo.td:2583

    defm LDR  : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>;

and then we have in ARMInstrInfo.td:1807

    multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
               InstrItinClass iir, PatFrag opnode> {

       ...
      def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins
ldst_so_reg:$shift),
                      AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
                     [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
       ...


The operand(s) to this instruction has to match `ldst_so_reg`, which
eventually is
done in `ARMDAGToDAGISel::SelectLdStSOReg`.
So my approach was to rearrange the operands, so
`ARMDAGToDAGISel::SelectLdStSOReg` can
find what it is looking for.

~chill