[llvm-dev] Questions about code-size optimizations in ARM backend

[Gabor Ballabas via llvm-dev]

Hi All,

I started to work on code-size improvements on ARM target by comparing 
GCC and LLVM generated code.
My first candidate was switch-case lowering.
I also created a Bugzilla issue for this topic: 
https://bugs.llvm.org/show_bug.cgi?id=34902
The full example code and the generated assembly for GCC and for LLVM is 
in the Bugzilla issue.

My first idea was to simplify the following instruction pattern
*lsl     r0, r0, #2**
**       ldr     pc, [r0, r1]*
to this:
*ldr     pc, [r1, r0, lsl #2]*

but then I got really confused when I started to look into the 
machine-dependent optimization passes in the backend.

I get a dump with the '-print-machineinstrs' option from the 
MachineFunctionPass and I can see these instructions in the beginning of 
the passes

*%vreg2<def> = MOVsi %vreg1, 18, pred:14, pred:%noreg, opt:%noreg; 
GPR:%vreg2,%vreg1**
**    %vreg3<def> = LEApcrelJT <jt#0>, pred:14, pred:%noreg; GPR:%vreg3**
**    BR_JTm %vreg2<kill>, %vreg3<kill>, 0, <jt#0>; mem:LD4[JumpTable] 
GPR:%vreg2,%vreg3*

and these at the end

*%R0<def> = MOVsi %R0<kill>, 18, pred:14, pred:%noreg, opt:%noreg**
**    %R1<def> = LEApcrelJT <jt#0>, pred:14, pred:%noreg**
**    BR_JTm %R0<kill>, %R1<kill>, 0, <jt#0>; mem:LD4[JumpTable]*

So basically I want to catch the pattern with the possible 
simplification using the shifter,
but I'm not even sure that I am looking into this issue at the right 
optimization level.
Maybe this idea should be implemented in a higher level, or as a fixup 
in ARMConstantIslands,
like the Thumb jumptable optimizations mentioned in the Bugzilla issue.

I hope someone more familiar with this part of the backend can give me 
some pointers about how to proceed with this idea
( or why it is complete rubbish in the first place :) )


Best regards,

Gabor Ballabas
Software Developer
Department of Software Engineering,
University of Szeged,
Hungary

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