[llvm-dev] REG_SEQUENCE use question

[Matt Arsenault via llvm-dev]

On 03/22/2017 08:17 AM, Peter Bel via llvm-dev wrote:
> Hi all,
>
> Can someone please explain me how to use REG_SEQUENCE in tablegen?
> The arch i'm writing backend for has 32-bit regs, and it has a couple 
> of 64-bit load/store instructions which use two neighboring regs at 
> once, which i'm trying to employ using virtual regs with subs.
>
> For example, it I want to move one 64-bit virtual reg to another, I'm 
> trying to use the following pattern:
>
> def LoReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), 
> isub_lo)>;
> def HiReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), 
> isub_hi)>;
> def MOVi64rr : Pat<(set GPR64:$Rd, GPR64:$Rn), \
'set' isn't something you can have in an input pattern. It is for 
assigning a result to a register, it isn't a DAG operation you can match 
against. You might be looking for bitconvert?

-Matt