[llvm-dev] REG_SEQUENCE use question

[Peter Bel via llvm-dev]

Hi all,

Can someone please explain me how to use REG_SEQUENCE in tablegen?
The arch i'm writing backend for has 32-bit regs, and it has a couple of
64-bit load/store instructions which use two neighboring regs at once,
which i'm trying to employ using virtual regs with subs.

For example, it I want to move one 64-bit virtual reg to another, I'm
trying to use the following pattern:

def LoReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_lo)>;
def HiReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_hi)>;
def MOVi64rr : Pat<(set GPR64:$Rd, GPR64:$Rn),
    (REG_SEQUENCE GPR64,
    (MOVi32rr (HiReg GPR64:$Rn)),
    isub_hi,
    (MOVi32rr (LoReg GPR64:$Rn)),
    isub_lo)>;

isub_hi and isub_lo are subregs of a single 64-bit virtual reg.

When trying to compile it, im getting the following error:
MOVi64rr:       (set GPR64:i64:$Rd, GPR64:i64:$Rn)
MOVi64rr:       (REG_SEQUENCE:<empty> GPR64:i32, (MOVi32rr:i32
(EXTRACT_SUBREG:i32 GPR64:i64:$Rn, isub_hi:i32)), isub_hi:i32,
(MOVi32rr:i32 (EXTRACT_SUBREG:i32 GPR64:i64:$Rn, isub_lo:i32)), isub_lo:i32)
error: In MOVi64rr: Could not infer all types in pattern result!
Assertion `SDNodes.count(R) && "Unknown node!"' failed.

If i'll specify the type for REG_SEQUENCE, i.e. (i64 (REG_SEQUENCE ...)),
it doesn't say anything about types, but it fails exactly at the same place
with Assertion `SDNodes.count(R) && "Unknown node!"' failed.

Thanks,
Petr
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