[llvm-dev] llvm-stress crash

[Hal Finkel via llvm-dev]

On 03/14/2017 09:37 AM, Jonas Paulsson via llvm-dev wrote:
> Hi,
>
> Using llvm-stress, I got a crash after Post-RA pseudo expansion, with 
> machine verifier.
>
> A 128 bit register
>
> %vreg233:subreg_l32<def,read-undef> = LLCRMux %vreg119; 
> GR128Bit:%vreg233 GRX32Bit:%vreg119
>
> gets spilled:
>
> %vreg265:subreg_l32<def,read-undef> = LLCRMux %vreg119; 
> GR128Bit:%vreg265 GRX32Bit:%vreg119
> ST128 %vreg265, <fi#10>, 0, %noreg; mem:ST16[FixedStack10](align=8) 
> GR128Bit:%vreg265
>
> -> regalloc
>
> %R5L<def> = LLCRMux %R6L, %R4Q<imp-def>
> ST128 %R4Q<kill>, <fi#10>, 0, %noreg; mem:ST16[FixedStack10](align=8)
>
> -> pseudo expansion
>
> %R5L<def> = LLCR %R6L
> STG %R4D<kill>, %R15D, 200, %noreg; mem:ST16[FixedStack7](align=8)
> STG %R5D<kill>, %R15D, 208, %noreg; mem:ST16[FixedStack7](align=8)
>
> *** Bad machine code: Using an undefined physical register ***
> - function:    autogen_SD29355
> - basic block: BB#19 CF257 (0x4cb6b00)
> - instruction: STG
> - operand 0:   %R4D<kill>
>
> So, it seems that vreg233 had only the low 64 bits defined to begin 
> with, the upper 64 are undefined.
> Then this interval is spilled with the ST128 pseudo. After expansion, 
> both 64 bit parts are spilled,
> where naturally the upper half is undefined.
>
> I wonder how this should be resolved. It seems there should be some 
> flag (read-undef?) on the ST128 or something after Virtual Register 
> Rewriter.
>
> Or is the target actually supposed to check liveness of register 
> during post-RA pseudo expansion?

Yes, in the sense that you shouldn't introduce uses of undefined 
physical registers. This seems like somewhat of a special case (in that 
you're taking an input register and breaking it up into subregisters 
explicitly). Avoiding inserting the store here also seems like a useful 
optimization. That having been said, you can force the register to be 
defined. I recall doing something similar in the PowerPC backend in the 
CR-bit spilling code -- in lib/Target/PowerPC/PPCRegisterInfo.cpp 
there's this:

   BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
           getCRFromCRBit(SrcReg))
           .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));


  -Hal

>
> /Jonas
>
> bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs
>
>
>
>
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-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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