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<div class="moz-cite-prefix">On 03/14/2017 09:37 AM, Jonas Paulsson
via llvm-dev wrote:<br>
</div>
<blockquote
cite="mid:9b1d37ae-93b2-3d07-ef4b-4913295afac7@linux.vnet.ibm.com"
type="cite">Hi,
<br>
<br>
Using llvm-stress, I got a crash after Post-RA pseudo expansion,
with machine verifier.
<br>
<br>
A 128 bit register
<br>
<br>
%vreg233:subreg_l32<def,read-undef> = LLCRMux %vreg119;
GR128Bit:%vreg233 GRX32Bit:%vreg119
<br>
<br>
gets spilled:
<br>
<br>
%vreg265:subreg_l32<def,read-undef> = LLCRMux %vreg119;
GR128Bit:%vreg265 GRX32Bit:%vreg119
<br>
ST128 %vreg265, <fi#10>, 0, %noreg;
mem:ST16[FixedStack10](align=8) GR128Bit:%vreg265
<br>
<br>
-> regalloc
<br>
<br>
%R5L<def> = LLCRMux %R6L, %R4Q<imp-def>
<br>
ST128 %R4Q<kill>, <fi#10>, 0, %noreg;
mem:ST16[FixedStack10](align=8)
<br>
<br>
-> pseudo expansion
<br>
<br>
%R5L<def> = LLCR %R6L
<br>
STG %R4D<kill>, %R15D, 200, %noreg;
mem:ST16[FixedStack7](align=8)
<br>
STG %R5D<kill>, %R15D, 208, %noreg;
mem:ST16[FixedStack7](align=8)
<br>
<br>
*** Bad machine code: Using an undefined physical register ***
<br>
- function: autogen_SD29355
<br>
- basic block: BB#19 CF257 (0x4cb6b00)
<br>
- instruction: STG
<br>
- operand 0: %R4D<kill>
<br>
<br>
So, it seems that vreg233 had only the low 64 bits defined to
begin with, the upper 64 are undefined.
<br>
Then this interval is spilled with the ST128 pseudo. After
expansion, both 64 bit parts are spilled,
<br>
where naturally the upper half is undefined.
<br>
<br>
I wonder how this should be resolved. It seems there should be
some flag (read-undef?) on the ST128 or something after Virtual
Register Rewriter.
<br>
<br>
Or is the target actually supposed to check liveness of register
during post-RA pseudo expansion?
<br>
</blockquote>
<br>
Yes, in the sense that you shouldn't introduce uses of undefined
physical registers. This seems like somewhat of a special case (in
that you're taking an input register and breaking it up into
subregisters explicitly). Avoiding inserting the store here also
seems like a useful optimization. That having been said, you can
force the register to be defined. I recall doing something similar
in the PowerPC backend in the CR-bit spilling code -- in
lib/Target/PowerPC/PPCRegisterInfo.cpp there's this:<br>
<br>
BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),<br>
getCRFromCRBit(SrcReg))<br>
.addReg(SrcReg,
getKillRegState(MI.getOperand(0).isKill()));<br>
<br>
<br>
-Hal<br>
<br>
<blockquote
cite="mid:9b1d37ae-93b2-3d07-ef4b-4913295afac7@linux.vnet.ibm.com"
type="cite">
<br>
/Jonas
<br>
<br>
bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs
<br>
<br>
<br>
<br>
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<br>
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</pre>
</blockquote>
<br>
<pre class="moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
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