[llvm-dev] Purpose of various register classes in X86 target
Arvind via llvm-dev
llvm-dev at lists.llvm.org
Thu Jul 27 22:47:44 PDT 2017
On 28 July 2017 at 04:13, Matthias Braun <mbraun at apple.com> wrote:
> It's not that hard in principle:
> - A register class is a set of registers.
> - Virtual Registers have a register class assigned.
> - If you have register constraints (like x86 8bit operations only work on
> al,ah,etc.) then you have to create a new register class to express that.
> (The only exception being limited to a single register, which instead we
> express by assigning the physreg directly instead of using a vreg).
> - Tablegen may create more regsiter classes for register coalescing where
> we want to accomodate constraints of multiple instructions at the same time.
> - All the information is in the .td file; you just have to put some effort
> into learning tablegen as the information is often expressed by using
> functions (i.e. the use add/sub/rotate/etc.) instead of just writing a
> table/list of registers).
Thanks a lot for the response! The TableGen language is fairly
straightforward(at least commands used in X86 td file). However, some of
the comments about the classes didn't fully make sense: I suppose the
constraints are probably derived from the X86 assembly language and I
should look there? In addition, some classes don't have any comments(eg:
GR64_TCW64) and I couldn't find much info elsewhere.
Also, I don't know how the TableGen'erated classes are derived. Would
reading TableGen's code help understand why those were generated and what
constraints they encode? Or should I take another approach?
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