[llvm-dev] Purpose of various register classes in X86 target
Matthias Braun via llvm-dev
llvm-dev at lists.llvm.org
Thu Jul 27 15:43:23 PDT 2017
It's not that hard in principle:
- A register class is a set of registers.
- Virtual Registers have a register class assigned.
- If you have register constraints (like x86 8bit operations only work on al,ah,etc.) then you have to create a new register class to express that. (The only exception being limited to a single register, which instead we express by assigning the physreg directly instead of using a vreg).
- Tablegen may create more regsiter classes for register coalescing where we want to accomodate constraints of multiple instructions at the same time.
- All the information is in the .td file; you just have to put some effort into learning tablegen as the information is often expressed by using functions (i.e. the use add/sub/rotate/etc.) instead of just writing a table/list of registers).
> On Jul 27, 2017, at 2:54 AM, Arvind via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> Hello everyone,
> I noticed that there are several register classes defined in X86 target and many of them are overlapping. Is there a list of all X86 register classes documented somewhere? I found many listed in X86GenRegisterInfo.inc(generated by tablegen) but unsure if that is the complete list. Also, is there documentation on the role and purpose of these classes and how the X86 backend decides which class to choose when generating machine code? The comments in X86RegisterInfo.td didn't help much to fully understand and I wasn't sure where to start reading the RegisterAllocator source code to understand how it uses the register classes.
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