[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
Craig Topper via llvm-dev
llvm-dev at lists.llvm.org
Wed Jul 19 15:02:45 PDT 2017
Can you send the generated registerinfo.inc file as well.
On Wed, Jul 19, 2017 at 2:47 PM, hameeza ahmed <hahmed2305 at gmail.com> wrote:
> I have made changes in 3 files:
> LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached
> Now i am getting following errors. which means registerinfo.inc file is
> not generated successfully.
> /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error:
> no member named 'XMM8' in namespace 'llvm::X86'
> if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
> fatal error: too many errors emitted, stopping now [-ferror-limit=]
> 20 errors generated.
> When i comment out the line to construct 65536 bit register in
> registerinfo.td. it run fine.
> What to do?
> On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek <
> kparzysz at codeaurora.org> wrote:
>> Those couldn't be done generically, that's why the asserts were added.
>> On 7/19/2017 4:30 PM, Craig Topper wrote:
>>> What about the static asserts protecting a Log call and another in the
>>> On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek <
>>> kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote:
>>> On 7/19/2017 4:18 PM, Craig Topper wrote:
>>> > LaneMask isn't as self contained as it should be. 64 bits is
>>> > here. The problem is accidental leaking of the current size.
>>> > For example there was a hard coded compare with 32 in tablegen
>>> until I
>>> > fixed it recently.
>>> This is most likely the only example. I actually tested it with
>>> uint64_t (but without exceeding 32 lanes).
>>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>>> hosted by The Linux Foundation
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
>> by The Linux Foundation
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