[llvm-dev] Deprecating the experimental microMIPS64R6 backend

[Simon Dardis via llvm-dev]

> -----Original Message-----
> From: Dr D. Chisnall [mailto:dc552 at hermes.cam.ac.uk] On Behalf Of David
> Chisnall
> Sent: 13 July 2017 11:22
> To: Simon Dardis
> Cc: llvm-dev at lists.llvm.org
> Subject: Re: [llvm-dev] Deprecating the experimental microMIPS64R6
> backend
> 
> On 13 Jul 2017, at 11:14, Simon Dardis via llvm-dev <llvm-dev at lists.llvm.org>
> wrote:
> >
> >
> > Hi all,
> >
> > I plan to deprecate the experimental microMIPS64R6 backend for the 5.0
> > release and remove it after the release.
> >
> > Currently there are no CPUs that use that particular sub-ISA which
> > makes it difficult to justify the maintenance and parallel development
> effort.
> >
> > If there was a CPU design produced that did use microMIPS64R6, the
> > backend could be restored from the archive.
> >
> > Any comments or objections?
> 
> Are there any microMIPS or MIPS16 CPUs in the wild?  There is a lot of
> complexity in the MIPS back end to handle these, but I’ve never seen one
> (and support for the far more common MIPS IV CPUs has suffered as a result
> of the back end focusing on these variants).
> 
> David

The Microchip PIC32 family[1] support microMIPS, the m62xxx cpus support
microMIPS32R6[2] and the interAptiv[3] series of chips support MIPS16. All are
currently available.

If you're aware  of any bugs or existing ones for the MIPS backend that need
addressing, can you bring them to my attention?

Thanks,
Simon

[1] http://ww1.microchip.com/downloads/en/DeviceDoc/61192A.pdf
[2] https://www.imgtec.com/mips/warrior/m-class-m6200-and-m6250-processor-cores/
[3] https://www.imgtec.com/mips/aptiv/interaptiv/ (datasheet, page 2)