[llvm-dev] RFC: Implement variable-sized register classes

[Krzysztof Parzyszek via llvm-dev]

On 9/26/2016 7:03 PM, Alex Elsayed via llvm-dev wrote:
> In such a design, it's very likely that the width of the registers in the
> vector processor may change between individual stripmine loops - that is,
> in fact, rather the point.

This proposal only deals with situations where the register size remains 
constant (and is known) at compile-time. It aims at reducing duplication 
of instruction definitions and selection patterns.

The case with the V extension for RISC-V and the VLA for ARM is 
different in a way that the register size is neither a compile-time 
constant, nor is it known. Handling of that would require a different 
set of changes in the compiler.

-Krzysztof

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