[llvm-dev] RFC: Implement variable-sized register classes

[Alex Elsayed via llvm-dev]

On Fri, 23 Sep 2016 13:01:47 -0700, Sean Silva via llvm-dev wrote:

> On Tue, Sep 20, 2016 at 10:32 AM, Krzysztof Parzyszek via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
> 
>> I have posted a patch that switches the API to one that supports this
>> (yet non-existent functionality) earlier:
>> https://reviews.llvm.org/D24631
>>
>> The comments from that were incorporated into the following RFC.
>>
>>
>> Motivation:
>>
>> Certain targets feature "variable-sized" registers, i.e. a situation
>> where the register size can be configured by a hardware switch.  A
>> common instruction set would then operate on these registers regardless
>> of what size they have been configured to have.

<snip>


One thing I'll note is that the RISC-V "V" (Vector) extension is likely 
to work this feature very hard indeed - see the following papers/slides/
talks:

"A Case for MVPs: Mixed-Precision Vector Processors"
http://hwacha.org/papers/hwacha-mvp-prism2014.pdf

"2nd RISC-V Workshop: Vector Extension Proposal"
http://riscv.wpengine.com/wp-content/uploads/2015/06/riscv-vector-
workshop-june2015.pdf
https://youtu.be/NlZr19lFxRg

In such a design, it's very likely that the width of the registers in the 
vector processor may change between individual stripmine loops - that is, 
in fact, rather the point.