[llvm-dev] Disabling Sparc (or other) back-end Floating Point registers

[Stefan Teleman via llvm-dev]

On Fri, Mar 11, 2016 at 7:20 AM, Chris.Dewhurst via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> I'm trying to estimate the work involved in disabling floating point
> registers on a Sparc back-end.
>
> Currently, I'm not sure how one would go about this. I can't identify
> equivalent examples in other processor back-ends.
>
> The desire is that the compiler is still able to handle floating-point
> operations, but utilizing only integer registers and software floating point
> support, without using any functions of the processor's FPU - instructions
> or registers.
>
> Clearly, disabling FP registers is only the start. The bigger task is
> getting floating point operations to use the integer registers after that.
>
> Can anyone give any direction on how one might go about this task?


Define another Target, which isn't Sparc, is 32-bit only, and doesn't
have FP registers and/or FP instructions.

It's going to be very difficult to do this inside the existing Sparc
Target. You run the risk of breaking the existing Sparc target, while
never getting Leon3 - or whatever it is that you're working on  - to
work correctly.

Much easier starting with a new, clean Target.

--Stefan

-- 
Stefan Teleman
KDE e.V.
stefan.teleman at gmail.com