[llvm-dev] Disabling Sparc (or other) back-end Floating Point registers

[Chris.Dewhurst via llvm-dev]

I'm trying to estimate the work involved in disabling floating point registers on a Sparc back-end.

Currently, I'm not sure how one would go about this. I can't identify equivalent examples in other processor back-ends.

The desire is that the compiler is still able to handle floating-point operations, but utilizing only integer registers and software floating point support, without using any functions of the processor's FPU - instructions or registers.

Clearly, disabling FP registers is only the start. The bigger task is getting floating point operations to use the integer registers after that.

Can anyone give any direction on how one might go about this task? I'm not even sure if this is the most pertinent question, but what I think would need to be known, as a start, is "How do you get all floating point values loaded into integer registers rather than floating point registers?"

Best Regards,
Chris Dewhurst, LERO, University of Limerick.
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