[llvm-dev] [Proposal][RFC] Cache aware Loop Cost Analysis

[JF Bastien via llvm-dev]

>
>
> A primary drawback in the above patch is the static use of Cache Line
> Size. I wish to get this data from tblgen/TTI and I am happy to submit
> patches on it.
>
> Yes, this sounds like the right direction. The targets obviously need to
> provide this information.
>

I'd like to help review this as it'll be necessary to implement
http://wg21.link/p0154r1 which is (likely) in C++17. It adds two
values, constexpr
std::hardware_{constructive,destructive}_interference_size, because in some
configurations you don't have a precise cacheline size but rather a range
based on what multiple architectures have implemented for the same ISA. I
think you'll want something similar.
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