[llvm-dev] Update: Re: Looking for contributors to target LLVM for open-source, multi-core GP-GPU-Compute Engine and RISC CPU

[Jerry Harthcock via llvm-dev]

Dear Members,

The past couple days, the SYMPL repository has received several hundred
visitors and an number of inquires, including some who are not happy with
the use of the two words, "open source".  The purpose of this update is to
bring to your attention the "FloPoCo" "open source" license, since the
SYMPL GP-GPU-Compute engine and SYMPL RISC CPU presently employ
FloPoCo-generated floating-point operators.  Here is an excerpt from the
"open source" license posted at the FloPoCo website, which is managed by
Insa Lyon, France located at the following link
http://flopoco.gforge.inria.fr/:

"Distribution

FloPoCo is open-source. Contributions are welcome!

Installation instructions (including one-line install for Ubuntu) are
provided in the user manual
<http://flopoco.gforge.inria.fr/flopoco_user_manual.html>.

The intent of the authors is to distribute FloPoCo as free software (in the
FSF AGPL sense), while imposing that the source code generated by FloPoCo
is also free software (also AGPL-like). The (A)GPL doesn't seem to allow
that, so it seems we have to invent something.

Current state of the license is therefore "all right reserved", which just
means that the distribution terms are still being decided by the copyright
owners (a consortium of the employers of the authors).
If this is a problem for your application, we are ready to negociate a
commercial license: contact us <Florent.de.Dinechin %C3%A0 ens.lyon.fr>."

Best regards,

Jerry

On Wed, Jan 20, 2016 at 11:51 AM, Jerry Harthcock <sympl.gpu at gmail.com>
wrote:

> Dear LLVM and OpenMP Members,
>
> The purpose of this communication is to bring your attention to the
> availability of an open-source, multi-core GP-GPU-Compute engine, companion
> RISC CPU and RISC Coarse-Grained Scheduler (CGS), all three of them
> executing the same SYMPL ISA instruction-set (*see* press release below).
>
> LLVM, including cycle-accurate instruction-set simulator and debugger,
> still need to be targeted to support this ISA.  So if anyone would be
> interested in initiating a re-targeting project, let me know, as I am sure
> we can work out a horse-trade of some sort.
>
> SYMPL GP-GPU-Compute Engine and SYMPL 32-bit RISC CPU repository:
> https://www.github.com/jerry-D/SYMPL-GP-GPU-Compute-Engines
>
> Yours very truly,
>
> Jerry
>
> *For Immediate Release*
> *Open-Source, IEEE754-2008 Compliant, GP-GPU-Compute Engine gets 32-Bit
> RISC CPU and Coarse-Grained Scheduler that Execute Same Instruction-Set*
>
> Austin, TX--Designed for massively parallel, FPGA-accelerated, 32-bit
> single-precision floating-point applications, the SYMPL ISA open-source RTL
> library now includes not only the multi-core, interleaving multi-threading,
> GP-GPU-Compute engine, but also now includes both a 32-bit RISC CPU and
> 32-bit Coarse-Grained Scheduler (CGS) that execute the same instructions as
> the GP-GPU, making the CPU, GP-GPU and CGS combination the world's first
> and only RISC CPU, GP-GPU and CGS to feature a homogeneous instruction-set
> architecture.
>
> Presently available for free download at the SYMPL GP-GPU-Compute Engine
> repository at GitHub, the Verilog RTL library includes sythesizable Verilog
> RTL source-code for SYMPL CPU, GP-GPU, CGS models comprising the SYMPL CPU,
> one to sixteen GP-GPUs and one to four CGSs.  Configuring the design is
> easily done at the top level of the design--just follow the instructions
> located at bottom of the “read-me” file at the SYMPL GP-GPU-Compute Engine
> repository.
>
> <clip>
>
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