[llvm-dev] a bundle with one instruction

[Krzysztof Parzyszek via llvm-dev]

On 1/21/2016 4:53 PM, Rail Shafigulin wrote:
>
> Just to clarify, when you say MC form do you mean Hexagon Assembly?
> Apologies if the question seems silly. I've been working with LLVM only
> a few months.

No problem.  At some point the machine instructions represented by a 
class "MachineInstr" are transformed into a representation using class 
"MCInst".  This is the MC level I'm talking about.  It's the 
representation that the llvm-mc uses.

-Krzysztof

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