[llvm-dev] a bundle with one instruction

[Rail Shafigulin via llvm-dev]

>
> No problem.  At some point the machine instructions represented by a class
> "MachineInstr" are transformed into a representation using class "MCInst".
> This is the MC level I'm talking about.  It's the representation that the
> llvm-mc uses.
>
>
Do you mind pointing out where in the code this is happening?


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies

On Fri, Jan 22, 2016 at 6:35 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:

> On 1/21/2016 4:53 PM, Rail Shafigulin wrote:
>
>>
>> Just to clarify, when you say MC form do you mean Hexagon Assembly?
>> Apologies if the question seems silly. I've been working with LLVM only
>> a few months.
>>
>
> No problem.  At some point the machine instructions represented by a class
> "MachineInstr" are transformed into a representation using class "MCInst".
> This is the MC level I'm talking about.  It's the representation that the
> llvm-mc uses.
>
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
>



-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160216/7db278d1/attachment.html>