[llvm-dev] Assign different RegClasses to a virtual register based on 'uniform' attribute?

[Tom Stellard via llvm-dev]

On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote:
> Hi,
> 
> I am working on a new LLVM target for Intel GPU, which also has same kind
> of scalar/vector register classes used in AMDGPU target. Like for a i32
> virtual register, it will be held in scalar register if its value is
> uniform across a wavefront/warp, otherwise it will be in a vector register.
> Does AMDGPU already done this? I read the code, but I didn't figure out how
> to do this. Anybody has idea on this?
> 

In the AMDGPU backend we select everything we can to scalar
instructions, and then after instruction selection, we move
non-uniform values to the vector ALU.  This is done by
the SIFixSGPRCopiesPass, which relies heavily on
SIInstrInfo::moveToVALU().

-Tom

> - Ruiling