[llvm-dev] TableGen - Help to implement a form of gather/scatter operations for Mips MSA

[Will Lovett via llvm-dev]

Hi Alex,

I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need:

If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition.
It allows a PatFrag be passed into the avx512_gather multiclass definition.

Working backwards from here, the actual PatFrags passed into this are things like ‘mgatherv4i32’.  These are patterns that match a MaskedGatherSDNode for a particular data type.

MaskedGatherSDNode is the generic SD node that represents a predicated gather, which in turn was generated from Intrinsic::masked_gather in the IR (in SelectionDAGBuilder::visitMaskedGather)

If your MIPS instruction has a predicate, you will need to create MIPS tablegen that matches MaskedGatherSDNode.  If not, I guess you’ll need to create a new intrinsic that represents an unpredicted gather, and add appropriate uses of it during IR creation (such as in LoopVectorize, where masked gathers are created today)

Hope that helps,

Will Lovett



On 9 December 2016 at 01:52:48, Alex Susu via llvm-dev (llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>) wrote:

Hello.
I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and
scatter operations exist for Mips, named LVI and SVI, respectively.

Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector
instructions) gather and scatter operations?
If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE,
but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather
instructions only for the x86 processor - there, they defined new SDNodes called
GatherNode and ScatterNode.)

Thank you,
Alex
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