[llvm-dev] NEON FP flags

[Renato Golin via llvm-dev]

On 1 April 2016 at 15:27, James Greenhalgh <james.greenhalgh at arm.com> wrote:
>> However, -ffast-math / unsafe-math should include subnormal support.
>
> No, we only have the big hammer throughout the ARM back-end to
> enable/disable support for the RTL IR that the vectorizer looks for
> when pattern matching. That means you also get your reduction loops and
> friends potentially changing your IEEE-754 expectations. Something more
> fine-grained would be feasible, but there'd be a fair bit of work needed to
> upgrade the implementation. In GCC we either take the performance hit or
> you use the big hammer.

Ok, so I think it's sensible to take the same approach and discuss the
extra subnormal flag with GCC/Clang folks.

I'll rebase my original patch so that at least our behaviour is
consistent for now.



> Having read the bug reports (16275/16274?) I realise I should have
> mentioned Neon intrinsics in my original mail. These *are* available
> with the appropriate -mfpu/-mfloat-abi/-march flags, no matter whether
> your have -funsafe-math-optimizations, and always map to their instruction
> (the implementation for this is not neat, essentially we have two backend RTL
> patterns, one which is always available for intrinsics, one which is
> conditionally available for auto-vectorization).

That's what I was trying to say with the Int vs FP vs allow VFP
instructions, but failed miserably. But this is not relevant to this
discussion now (and we have similar issues lowering them :).

My change above will make the behaviour identical, so we can discuss
about the subnormal flag later.

Thanks!!

--renato