[llvm-dev] tracking known operand bits across passes

Smith, Kevin B via llvm-dev llvm-dev at lists.llvm.org
Wed Oct 28 14:18:41 PDT 2015

Time frame is within the next month.

My pass executes quite late in the CG, post RA, just a bit before it gets to encoding.  Specifically it is here:

void X86PassConfig::addPreEmitPass() {
  if (getOptLevel() != CodeGenOpt::None)

  if (UseVZeroUpper)

  if (getOptLevel() != CodeGenOpt::None) {
    addPass(createX86FixupBWInsts());                // This is the new pass for byte/word instruction optimization pass.

right now. No information is preserved.  It uses the register liveness information already present in the Machine Instructions IR.

Sorry, no I didn't intend to move this to llvm-commits.  Fat fingered that instead of llvm-dev with auto-completion in Outlook.  Moved back to llvm-dev.  Thanks for pointing that out.


-----Original Message-----
From: kingshizzle at gmail.com [mailto:kingshizzle at gmail.com] On Behalf Of Steve King
Sent: Wednesday, October 28, 2015 2:05 PM
To: Smith, Kevin B
Cc: llvm-commits at lists.llvm.org
Subject: Re: [llvm-dev] tracking known operand bits across passes

On Wed, Oct 28, 2015 at 12:08 PM, Smith, Kevin B
<kevin.b.smith at intel.com> wrote:
> I have a pass that can do what you want, but not by computing or using known bits.  I intend to try to upstream this
> for X86 CG.

Thanks!  Have a time frame in mind?

> It works by looking for byte and word operations that might be more profitably done either using movz(wb)l or by simply making
> the instruction larger.

When does your pass execute?  Do you preserve information between passes?

> But it does this not by knowing bits are zero or one, but by making sure the upper bits of the register are
> unused/dead. It could definitely do this for andw ->andl without much trouble at all.

Neat.  I wonder if known-bit tracking would enable enough additional
promotions to pay for the computing and tracking effort.

Also, did you mean to move this discussion to the commits mailing list?


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