[llvm-dev] [backend]two-address encoding in llvm tblgen

[Hal Finkel via llvm-dev]

----- Original Message -----
> From: "Xiaochu Liu via llvm-dev" <llvm-dev at lists.llvm.org>
> To: "LLVM Developers Mailing List" <llvm-dev at lists.llvm.org>
> Sent: Tuesday, November 24, 2015 5:08:49 PM
> Subject: [llvm-dev] [backend]two-address encoding in llvm tblgen
> 
> Dear there,
> 
> I'm developing an instruction layout like:
> 
> opcode | rd| ts
> 
> and its semantics is:
> 
> rd= rd opcode rs
> 
> But when I describe it in td file like this:
> 
> class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
> : InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr,
> "\t$rd, $rs"), Pattern> {
>   bits<5> rd;
>   bits<6> rs;
>   let Opcode=Op;
> }

You need to use a different input and output register, and then tie them together:

class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rdi, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
  bits<5> rd;
  bits<6> rs;
  let Opcode=Op;

  let Constraints = "$rdi = $rd";
  let DisableEncoding = "$rdi";
}

 -Hal

> 
> It complains for 'rd'. I was wondering if there is any standard way
> of
> doing this?
> 
> Thanks,
> Xiaochu
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> 

-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory