[llvm-dev] [backend]two-address encoding in llvm tblgen

[Xiaochu Liu via llvm-dev]

Dear there,

I'm developing an instruction layout like:

opcode | rd| ts

and its semantics is:

rd= rd opcode rs

But when I describe it in td file like this:

class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
  bits<5> rd;
  bits<6> rs;
  let Opcode=Op;
}

It complains for 'rd'. I was wondering if there is any standard way of
doing this?

Thanks,
Xiaochu