[llvm-dev] Hexagon, DFAPacketizer and instruction expansion

[Bruce Hoult via llvm-dev]

Sorry to butt in .. but curious ...

"a RET instruction which gets expanded into a write to a register and a
jump/branch"

If you do that after Register Allocation then where do you get the
temporary register from? Not knowing the architecture in question at all,
maybe there's a dedicated one, in which case fine. But if not?

On Thu, Nov 19, 2015 at 6:30 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> On 11/18/2015 6:02 PM, Rail Shafigulin wrote:
>
>>
>> I guess I should be more clear by what I mean "expanded". When I say
>> "expanded" I mean the final instruction assembly representation, i.e.
>> all instructions were lowered to their assembly level. Will you
>> recommendation still hold or I should be considering another approach?
>>
>
> For dealing with cases like the RET instruction you described
> earlier---yes, the post-RA pseudo instruction expansion is the right place
> to do it.
>
>
> -Krzysztof
>
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