[llvm-dev] DFAPacketizer assert failure

[Rail Shafigulin via llvm-dev]

For some reason on my VLIW target DFAPacketizer fails at

assert(CachedTable.count(StateTrans) != 0);

in the following function:

// reserveResources - Reserve the resources occupied by a MCInstrDesc and
// change the current state to reflect that change.
void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
  unsigned InsnClass = MID->getSchedClass();
  const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
  unsigned FuncUnits = IS->getUnits();
  UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
  ReadTable(CurrentState);
  assert(CachedTable.count(StateTrans) != 0);
  CurrentState = CachedTable[StateTrans];
}

This happens at the packetization stage, i.e. scheduling seems to work. My
schedule description is not very different from Hexagon or R600. I'm not
quite sure why this is happening. Would someone be able to shed some light
on this?

Any help is appreciated.

-- 
R
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