[llvm-dev] Instructions with no operand

[Sky Flyer via llvm-dev]

Guys, I stuck at this point. Could you please give me a hint how to solve
this problem without touching the LLVM backbone?!
Why LLVM doesn't let me define an instruction consisting of an operator
with no operand?

On Mon, Oct 19, 2015 at 5:04 PM, Sky Flyer <skylake007 at googlemail.com>
wrote:

> Hi all,
>
> I am trying to implement an instruction with no operand for example "clr"
> in TableGen.
>
> -----------------------------------------
> e.g.
>
> *InstrInfo.td:*
>
> class TestInst<string opc, string asmstr, dag oops, dag iops,
>                 list<dag> pattern> : Instruction { ... }
>
> def int_no_operand : Intrinsic<[]>;
> class ALU<string opc> : TestInst<opc, "", (outs), (ins),
> [(int_no_operand)]>;
>
> *InstrFormat.td*
> multiclass Clr {
>  def _ : ALU<"clr">
>    {let InstOp  = 0b11;}
> }
>
> -----------------------------------------
>
> after compiling the code, I receive the following error:
>
>
>
> *llvm-tblgen: /llvm/utils/TableGen/CodeGenInstruction.h:186:
> std::pair<unsigned int, unsigned int>
> llvm::CGIOperandList::getSubOperandNumber(unsigned int) const: Assertion `i
> < OperandList.size() && "Invalid flat operand #"' failed.*
>
>
> How can I define an instruction with no operand?
> In ARM there is a similar instruction like "CLREX" but I don't understand
> why in the assertion in CodeGenInstruction.h number of sub operand num
> should be more than 0? getSubOperandNumber counts the operator (i.e. the
> instruction mnemonic itself) as well? I mean, we will have minimum 1 in any
> situation or it's just the number of operators?!
>
> Cheers,
> ES
>
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