[LLVMdev] "Node emitted out of order - late" assertion failure

[deadal nix]

Whenever I'm doing something like :

    const TargetRegisterClass *RC = getRegClassFor(RegVT);
    unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);

    Chain = DAG.getCopyToReg(Chain, DL, VReg, Val);
    Val = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
    Chain = Val.getValue(1);

I end up getting assertion failure about node being emited out of order :

unsigned int llvm::InstrEmitter::getVR(llvm::SDValue,
DenseMap<llvm::SDValue, unsigned int> &): Assertion `I != VRBaseMap.end()
&& "Node emitted out of order - late"' failed.

What does it mean and how do I fix it ?
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