[LLVMdev] Register Allocation on IR

[Renato Golin]

On 17 June 2015 at 18:05, Matthias Braun <mbraun at apple.com> wrote:
> Having worked on SSA register allocators in the past I have to say that SSA is actually a good fit for register allocation. However LLVM IR is indeed not. You don't have any target instructions or register classed/constraints. It wouldn't make much sense to designate registers to llvm IR values nor is there a way to express that in IR. llvm has the machine instruction (MI) representation for that.

If I got it right, the intention here is to do simulations in IR. I'm
assuming this is some form of cost function that instead of executing,
would try to predict what would happen if it did run, without running.
For that, doing some form of register allocation in IR can actually be
beneficial from the register pressure point of view.

You could even do that in a generic way by just passing the ABI
register allocation first (what we do during lowering/legalization)
and then just letting the simulator know how many GPRs there are, and
the simulator can then estimate register pressure in basic blocks or
functions by using a poor-man's version of liveness analysis on the
remaining SSA registers in the sub-graph.

While this would be an interesting project, I can't see this being an
integral part of the LLVM codebase, as it would mess up the IR beyond
recognition by current back-ends.

cheers,
--renato