[LLVMdev] Register Allocation on IR

[Matthias Braun]

Having worked on SSA register allocators in the past I have to say that SSA is actually a good fit for register allocation. However LLVM IR is indeed not. You don't have any target instructions or register classed/constraints. It wouldn't make much sense to designate registers to llvm IR values nor is there a way to express that in IR. llvm has the machine instruction (MI) representation for that.

- Matthias

> On Jun 17, 2015, at 5:37 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote:
> 
> On 15 Jun 2015, at 17:21, Kartik Ramkrishnan <kartikram3 at gmail.com> wrote:
>> 
>> Thanks. I will also work on doing an SSA register allocation that returns SSA form (IR), since it is not yet implemented.
> 
> It’s not implemented because it doesn’t really make sense as a concept.  Register allocation is all about making use of a finite set of registers, spilling values to memory if they don’t fit.  In SSA form, you have an infinite number of registers and (more importantly) you can only assign to each register once, so there is no way of spilling from a register and then using that register for something else.
> 
> To implement register allocation in LLVM IR, you would need IR not to be SSA, and then it wouldn’t be LLVM IR.
> 
> David
>